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Application Note 9611
voltage level as previously mentioned. When the triangle wave
reaches a minimum, a positive rising pulse is output at pin 3 of
the ICM7555 timer, U 8 . This rising edge ‘clocks’ the U 5A flip-
flop which will either result in a high level at U 5A ’s Q or QNOT
2
1
C2 FREQ.
110.04Hz
outputs, depending on the state of the data, D, input pin. It is
not important which goes high first, only that the toggling of
the Q and QNOT outputs of U 5A alternate at each positive
clock pulse from pin 3 of U 8 . The timer’s output, pin 3, goes
low each time that the triangle wave reaches a peak.
Of paramount importance, however, is the need to
synchronize the state of U 5B ’s Q and QNOT outputs with
those of U 5A . Arbitrarily the Q output of U 5A was chosen to
drive the upper left MOSFET in the left half-bridge (QNOT
CH1 = 5V
CH2 = 2V
M = 2.5 μ s
GLITCH CH2
obviously drives the lower MOSFET). It is necessary that
FIGURE 6. SECONDARY-SIDE CONTROL WAVEFORMS WITH
LOWER DC BUS VOLTAGE
C2 FREQ.
55.552Hz
2
1
whenever the upper MOSFET of the left half-bridge is gated
that the lower MOSFET in the right half-bridge also will be
gated sometime within the same half-cycle. To guarantee that
this happens it is necessary to connect either the Q or QNOT
output of U 5A to the data, D, input of U 5B . If the Q output of
U 5A , which corresponds to the upper left MOSFET gate drive,
is chosen to drive the D input of U 5B , the next clock pulse from
the phase-shifted clock which goes to U 5B ’s clock input pin
must gate the lower right MOSFET, which corresponds to the
LIN input of the right half-bridge driver, U 9 . Therefore the Q
output signal of U 5B must drive the LIN input of U 9 and the
QNOT signal of U 5B must drive the HIN input of U 9 .
The waveforms in Figure 4 show the phase voltage
waveforms of the left and right half-bridges and the resulting
output voltage waveform shown in Figure 3. Notice that the
algebraic difference between Trace 2 and Trace 1 waveforms
CH1 = 5V
CH2 = 5V
M = 2.5 μ s
GLITCH CH2
precisely result in a waveform like that of Figure 3.
2
1
FIGURE 7. SECONDARY-SIDE FLIP-FLOP WAVEFORMS
C2 FREQ.
55.872Hz
Unlike the HIP4082 and other members of the HIP408X
family, the HIP2500 high voltage half-bridge driver requires
external circuitry to insure that the upper and lower
MOSFETs in a half-bridge leg do not conduct
simultaneously. The quad AND-gate, U 6 , and resistors R 24 -
R 27 , and capacitors C 14 -C 17 tailor the dead-time to the
needs of any application. Each Q and QNOT output from the
flip-flops go directly to one input of a two input AND-gate and
also through an R-C delay to the 2nd input of the AND-gate.
Only after the R-C delay can the output of an AND-gate go
high. Conversely, when any of the Q or QNOT outputs go
low, a zero is placed on one of the AND-gate inputs and the
AND-gate’s output immediately goes low. Therefore an ON-
DELAY is produced, but no corresponding OFF-DELAY is
produced.
CH1 = 5V
CH2 = 5V
M = 2.5 μ s
GLITCH CH2
Overcurrent Protection
FIGURE 8. HIP2500 INPUT WAVEFORMS
The left and right half side half-bridges must be synchronized.
The left half-bridge switching is perfectly synchronized with
the minimum instances of the triangle wave and is therefore
fixed in phase with the triangle wave. The right half-bridge
slides with the level of the signal proportional to the DC bus
7
An instantaneous overcurrent function senses the voltage
drop across R 23 for the purposes of shutting down the
secondary-side inverter. The circuit comprising U 7A , R 28 ,
R 29 , R 32 , R 36 , shunt resistor R 23 and capacitor, C 32 dictate
the current trip level. The values shown in the schematic
should cause overcurrent trip at approximately 1.3A. The
voltage on the negative summing junction of U 7A dictates the
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